DragonX/drg-xmrig
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2,344 Commits 1 Branch 3 Tags
87bcad16711754f4a009f34a239ba869229a29ee
Commit Graph
1581 Commits
Author SHA1 Message Date
XMRig 20c3c03501 Merge branch 'dev' of github.com:xmrig/xmrig into dev 2020-08-26 16:11:48 +07:00
XMRig 6bd6977df1 Fix colors on macOS. 2020-08-26 16:11:29 +07:00
SChernykh 1dca648537 Fixed self-select login sequence 
In self-select mode, we only have pool wallet right after login.
 2020-08-25 16:17:48 +02:00
XMRig e254283089 Fix compile warnings. 2020-08-24 10:04:46 +07:00
XMRig 04f3abb4e2 Improved CUDA loader error reporting and fixed plugin load on Linux. 2020-08-23 21:30:12 +07:00
XMRig eb9f98b8ce Better scripts/build.*.sh compatibility. 2020-08-23 15:46:56 +07:00
XMRig 42576e91dc Fix compile warning. 2020-08-23 14:22:08 +07:00
XMRig 1ca51c84e8 Fixed tag in OclLib. 2020-08-21 08:21:51 +07:00
XMRig 5850a2aa26 Disable GPU backends with static build on Linux. 2020-08-20 15:02:31 +07:00
XMRig 87a3345fb5 v6.3.3-dev 2020-08-20 13:54:52 +07:00
XMRig 9216c656b6 v6.3.2 2020-08-20 12:54:22 +07:00
XMRig a99906b667 Merge branch 'battery-macos' of https://github.com/jtgrassie/xmrig into dev 2020-08-20 12:46:09 +07:00
XMRig 3baf926bb7 Fix compile warning 2020-08-17 06:08:14 +07:00
XMRig 25d8c2f2f3 Always use all available threads on ARM. 2020-08-16 17:36:38 +07:00
XMRig e5e5b48216 Fixed compile warning and updated build.uv.sh. 2020-08-16 16:03:27 +07:00
XMRig 5aecbff89a Merge branch 'dev' of github.com:xmrig/xmrig into dev 2020-08-16 15:47:57 +07:00
XMRig 0f7ae874e0 Added ARM CPU name detection based on lscpu code. 2020-08-16 15:47:29 +07:00
SChernykh 07d9abc90e RandomX JIT: optimized address mask calculation 2020-08-12 16:45:16 +02:00
Jethro Grassie 1de4e4ddfd fix macos battery detection 2020-08-11 18:04:56 -04:00
XMRig 660096ebb5 Fixed rare protocol error in HTTP client. 2020-08-07 21:54:22 +07:00
XMRig d3ddb76962 Fixed RandomX cache initialization if 1GB pages fails to allocate on a first NUMA node. 2020-08-01 12:30:02 +07:00
xmrig fbf78d2789 Merge pull request #1794 from SChernykh/dev 
More robust 1 GB pages handling
 2020-07-31 20:45:27 +07:00
SChernykh 3d78f30171 Try to allocate scratchpad from dataset's 1 GB huge pages, if normal huge pages are not available 2020-07-31 13:37:22 +02:00
XMRig 5ce47b764d v6.3.2-dev 2020-07-31 16:50:23 +07:00
SChernykh 5aae95eddc Force 2 MB pages size in allocateLargePagesMemory() on Linux 2020-07-31 09:55:49 +02:00
XMRig 25797edb22 v6.3.1 2020-07-31 13:20:56 +07:00
XMRig 9829da5d4e Added command line option --pause-on-battery and renamed config option. 2020-07-23 15:45:01 +07:00
XMRig 7d65aa8ed7 Add tags 2020-07-23 10:26:56 +07:00
xmrig f478fa5e55 Merge pull request #1786 from SChernykh/dev 
Added mining on battery setting
 2020-07-23 09:20:06 +07:00
SChernykh 8c8a46acb8 Added mining on battery setting 2020-07-22 20:21:42 +02:00
XMRig b2b54cbe82 Cleanup 2020-07-22 21:27:40 +07:00
XMRig c5709e1822 Cleanup usage output. 2020-07-22 19:58:08 +07:00
SChernykh 51370682f3 Fixed RandomX initialization for VS debug builds 2020-07-21 10:10:07 +02:00
XMRig 3526c1335d Added command line options --cache-qos (--randomx-cache-qos) and --argon2-impl (--cpu-argon2-impl). 2020-07-20 09:17:59 +07:00
XMRig 8a2b91fbea v6.3.1-dev 2020-07-17 03:13:02 +07:00
XMRig b89d6da67d v6.3.0 2020-07-17 00:17:55 +07:00
XMRig 8a74126af9 v6.3.0-dev 2020-07-17 00:04:31 +07:00
XMRig 8c25eab8dd Sync changes with the proxy. 2020-07-16 23:29:21 +07:00
SChernykh 3180e242a9 Cryptonight OpenCL: fix for long input data 2020-07-16 10:39:32 +02:00
XMRig da244e7acf Fixed build without MSR support. 2020-07-16 05:15:35 +07:00
XMRig cab29e4103 Merge branch 'master' of https://github.com/haven-protocol-org/xmrig into haven-protocol-org-master 2020-07-15 23:33:17 +07:00
Neil Coggins 83bb040bf3 Increased max blob size to support Haven offshore capability 2020-07-14 11:52:43 +01:00
SChernykh e8dbb8ca9f Removed cache QoS warning at exit on unsupported CPUs 2020-07-13 20:43:49 +02:00
SChernykh a3f4d91ad7 Cache QoS: fix for seting MSR 2020-07-13 20:30:44 +02:00
SChernykh 5af50b854c RandomX: added cache QoS support 
False by default. If set to true, all non-mining CPU cores will not have access to L3 cache.
 2020-07-13 17:23:18 +02:00
Jim Huang 3343e373e8 Adopt new SSE2NEON and reduce ARM-specific changes 
This patch updated SSE2NEON [1], which contains more functions
provided by Intel intrinsics, only implemented with NEON-based
counterparts to produce the exact semantics of the intrinsics.
Consequently, ARM-specific changes against CryptoNight_arm can
be reduced as well.

[1] https://github.com/DLTcollab/sse2neon/
 2020-07-11 01:55:11 +08:00
XMRig 8726bf1494 v6.2.4-dev 2020-07-10 03:12:00 +07:00
XMRig 2f65f7f691 v6.2.3 2020-07-09 22:24:35 +07:00
SChernykh 08d71d5144 RandomX: tweaked Ryzen code 
Very small speedup
 2020-07-05 16:06:59 +02:00
xmrig 7a8fc700a2 Merge pull request #1763 from SChernykh/dev 
KawPow: fixed more duplicate share errors
 2020-07-04 02:37:03 +07:00