Commit Graph
276 Commits
Author SHA1 Message Date
XMRig dd0f924bff Added initial memory pool support. 2019-10-07 12:36:40 +07:00
XMRig 5058da3f29 Fixed exit. 2019-10-05 11:24:22 +07:00
XMRig 717e13818f Implemented RxNUMAStorage. 2019-10-05 08:24:28 +07:00
XMRig 93a70f4bbe Added RxNUMAStorage stub. 2019-10-04 18:43:03 +07:00
XMRig 473b98ae68 Extended "numa" option for RandomX. 2019-10-04 10:49:55 +07:00
XMRig f9f5b8a716 Added interface IRxStorage and RxBasicStorage class. 2019-10-04 08:45:13 +07:00
XMRig c452846a6a #1212 Fixed RandomX dataset re-initialization. 2019-10-02 06:35:49 +07:00
XMRig dea1f983f0 Merge branch 'dev' into evo 2019-10-01 07:26:18 +07:00
XMRig aaddfbe779 Fixed support for systems where total count of NUMA nodes not equal usable count. 2019-10-01 07:19:13 +07:00
XMRig 9c064cdeee Fixed excessive memory allocation. 2019-09-30 08:28:25 +07:00
XMRig 00851b9fb8 Added clRetainMemObject support. 2019-09-30 07:30:14 +07:00
XMRig dcb233ce91 RandomX dataset specific code moved into OclSharedData class. 2019-09-30 06:59:44 +07:00
XMRig 768f1d9269 Class OclInterleave renamed to OclSharedData and added class OclSharedState. 2019-09-30 05:18:53 +07:00
XMRig b89616fc8b Fixed ARM build. 2019-09-28 23:26:03 +07:00
XMRig 7dd790dfc2 Fixed build on macOS. 2019-09-28 18:20:56 +07:00
XMRig 255f6cff6b Added config option "cpu/max-threads-hint" and command line option "--cpu-max-threads-hint". 2019-09-28 02:02:20 +07:00
XMRig a718e241e7 Fixed build with gcc 4.8. 2019-09-27 01:55:05 +07:00
XMRig 68cec11663 Reduced PciTopology class size. 2019-09-27 01:03:37 +07:00
XMRig e5e2953ffe Added command line option --opencl-devices (hint mode) 2019-09-24 23:01:03 +07:00
XMRig c0d3d9686d Fixed potential truncation. 2019-09-24 00:03:50 +07:00
XMRig efd2e8d757 OpenCL backend disabled by default. 2019-09-23 05:51:46 +07:00
XMRig 096020e2a8 Add support for initialize OpenCL in runtime. 2019-09-23 05:33:48 +07:00
XMRig 477de6a212 Improved/restructured --help output. 2019-09-23 03:47:40 +07:00
XMRig 4120529057 Use more JS friendly names. 2019-09-23 01:27:05 +07:00
XMRig 314168eb44 Extended OpenCL threads information. 2019-09-22 02:10:14 +07:00
XMRig e9d7648fdb Added global backends hashrate to "GET /2/backends" endpoint. 2019-09-20 14:15:35 +07:00
XMRig 5cdcd1ebdc [opencl] Better cn/r specific resource management. 2019-09-19 03:42:11 +07:00
XMRig 2ddd0e2cd8 Fixes for Intel OpenCL platform. 2019-09-19 02:05:42 +07:00
XMRig b142a71573 #1177 Fixed unroll syntax for old drivers. 2019-09-18 23:46:51 +07:00
XMRig d1d0ed7fe2 Allow partially started threads. 2019-09-17 02:22:59 +07:00
XMRig 88fd722ad3 Simplify code. 2019-09-16 23:53:39 +07:00
XMRig 4223e282d6 Improved thread self test error message. 2019-09-16 01:27:51 +07:00
XMRig 26e3d541b2 Use RxAlgo:base instead of switch. 2019-09-14 12:00:33 +07:00
SChernykh a2b5acc127 RandomX config generator for OpenCL
Also fixed compilation errors on VS2019
2019-09-13 21:05:00 +02:00
XMRig a3e66e94cf Fix compile warning, mostly struct/class inconsistency. 2019-09-13 18:21:05 +07:00
XMRig a271f5d0be Fixed MSVC build. 2019-09-13 17:17:48 +07:00
XMRig eef7e72459 Use sub buffers. 2019-09-13 16:10:12 +07:00
XMRig d2cc7075d4 OclLib improvements. 2019-09-13 10:35:32 +07:00
XMRig dbce6a548b Added OpenCL code minification . 2019-09-12 18:50:35 +07:00
XMRig 43e7d13d3d Added autoconfig stub for RandomX. 2019-09-12 15:21:14 +07:00
XMRig 3afc880fe5 Implemented option "dataset_host". 2019-09-12 13:49:27 +07:00
XMRig 9428659e72 Implemented OpenCL JIT mode. 2019-09-12 13:10:50 +07:00
XMRig 204fb31d5b Cleanup. 2019-09-12 01:09:30 +07:00
XMRig e9b20fff81 Implemented VM mode for OpenCL RandomX. 2019-09-12 00:01:03 +07:00
XMRig c4b49d4213 OpenCL RandomX WIP 2019-09-11 15:48:02 +07:00
XMRig 9fb3f9e01c Initial RandomX source code prepare and compile. 2019-09-08 21:56:18 +07:00
XMRig 91fa0439d7 Added autoconfig for cn/gpu. 2019-09-08 16:28:51 +07:00
XMRig 7c772d733b Added basic cn/gpu support. 2019-09-08 08:59:17 +07:00
XMRig 05bd6839aa Fix for ROCm. 2019-09-07 09:46:50 +07:00
XMRig a05c40b7e2 Improved OpenCL startup time. 2019-09-06 21:48:15 +07:00