SChernykh
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5af50b854c
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RandomX: added cache QoS support
False by default. If set to true, all non-mining CPU cores will not have access to L3 cache.
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2020-07-13 17:23:18 +02:00 |
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SChernykh
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038629c093
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Print error message when MSR mod fails
Make sure user knows that hashrate is worse than it could be.
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2020-06-26 19:54:06 +02:00 |
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XMRig
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306dfe8d6a
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Use long tags.
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2020-05-28 20:32:41 +07:00 |
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XMRig
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5eed25d4aa
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Update year.
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2020-02-01 20:24:00 +07:00 |
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SChernykh
|
aac5ce39a4
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MSR preset for Bulldozer CPUs
Also fixed verbose output for MSR presets with masks.
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2020-01-14 19:27:34 +01:00 |
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SChernykh
|
07e36a6cf0
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Refactor Ryzen fix to fix compilation issues
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2019-12-31 11:55:07 +02:00 |
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XMRig
|
cbcf033ebe
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Code style cleanup.
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2019-12-28 01:45:54 +07:00 |
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SChernykh
|
a1f223dcb0
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Fix for 1st-gen Ryzen crashes
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2019-12-27 12:40:38 +02:00 |
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XMRig
|
ddcc9852f7
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Use MsrItem::kNoMask.
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2019-12-19 03:20:48 +07:00 |
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SChernykh
|
fc3c995ec2
|
Added bit masks for MSR registers
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2019-12-17 23:55:22 +01:00 |
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XMRig
|
59a3d8c530
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Added "verbose" option.
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2019-12-17 21:46:11 +07:00 |
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XMRig
|
9d67221f54
|
Added save/restore MSR registers on Linux.
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2019-12-17 16:17:11 +07:00 |
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XMRig
|
efb63d15e1
|
Added support for write custom MSR.
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2019-12-17 02:27:07 +07:00 |
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XMRig
|
6d9e1a50cc
|
Unified Linux/Windows MSR log messages.
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2019-12-15 01:32:41 +07:00 |
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XMRig
|
2f19cddc9f
|
Added additional MSR registers for Ryzen CPUs.
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2019-12-12 14:21:15 +07:00 |
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XMRig
|
6d176d2013
|
Fixed MSR.
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2019-12-11 20:09:25 +07:00 |
|
XMRig
|
7a507a2c8a
|
Added support for AMD specific MSR registers.
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2019-12-11 19:37:13 +07:00 |
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XMRig
|
f960d1cf16
|
Added RandomX option "wrmsr" with command line equivalent --randomx-wrmsr=N.
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2019-12-10 23:57:29 +07:00 |
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