SChernykh
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716df54ac0
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JIT compiler: removed unnecessary memcpy from generateProgram()
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2020-01-13 18:00:41 +01:00 |
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XMRig
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dc9df3d6ff
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v5.5.2-dev
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2020-01-12 12:55:50 +07:00 |
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XMRig
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e5492888d9
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v5.5.1
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2020-01-12 08:34:01 +07:00 |
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xmrig
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e940f27d76
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Merge pull request #1493 from SChernykh/dev
Update MSR preset for Intel
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2020-01-09 14:24:11 +07:00 |
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SChernykh
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b4b2a19b33
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Update MSR preset for Intel
As per https://github.com/xmrig/xmrig/issues/1433#issuecomment-572126184
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2020-01-09 08:10:36 +01:00 |
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XMRig
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4f4d08f518
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Code cleanup.
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2020-01-07 10:13:01 +07:00 |
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SChernykh
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a976379f19
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JIT compiler tweaks
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2020-01-06 13:57:48 +01:00 |
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XMRig
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7e1c208732
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Fix compile warnings.
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2020-01-03 19:11:48 +07:00 |
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XMRig
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954fe2cf78
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Merge branch 'dev' of github.com:xmrig/xmrig into dev
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2020-01-03 05:36:47 +07:00 |
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XMRig
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a2d1c5a371
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Fixed unwanted resume after dataset change.
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2020-01-03 05:36:22 +07:00 |
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SChernykh
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07e36a6cf0
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Refactor Ryzen fix to fix compilation issues
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2019-12-31 11:55:07 +02:00 |
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SChernykh
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58472d0674
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Cleanup
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2019-12-30 20:55:03 +02:00 |
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SChernykh
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467fbfdc77
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Auto-config for mobile Ryzen APUs
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2019-12-30 20:53:21 +02:00 |
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XMRig
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53938e1953
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v5.5.1-dev
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2019-12-30 16:05:51 +07:00 |
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XMRig
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6fe4d310fb
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#1469 Fixed build with gcc 4.8.
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2019-12-30 16:04:07 +07:00 |
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XMRig
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ac4f96525f
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v5.5.0
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2019-12-29 21:42:11 +07:00 |
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XMRig
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730f028343
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Add "cn/ultra" alias for tlo-pool.raasu.org pool.
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2019-12-29 15:36:05 +07:00 |
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XMRig
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d74775d702
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Added "cn-pico/tlo".
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2019-12-29 00:29:19 +07:00 |
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XMRig
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82d4a1b3c9
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Fix build.
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2019-12-28 02:00:08 +07:00 |
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XMRig
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cbcf033ebe
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Code style cleanup.
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2019-12-28 01:45:54 +07:00 |
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SChernykh
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a1f223dcb0
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Fix for 1st-gen Ryzen crashes
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2019-12-27 12:40:38 +02:00 |
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XMRig
|
c6dbffcb95
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Revert Platform::setProcessPriority
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2019-12-27 03:19:03 +07:00 |
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XMRig
|
a46c4f02e8
|
Removed "rx/v" algorithm.
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2019-12-26 22:34:19 +07:00 |
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XMRig
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94ea19ef2f
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v5.5.0-dev
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2019-12-25 04:53:38 +07:00 |
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XMRig
|
e7c4b1d0c2
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Fixed memory allocation checks.
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2019-12-25 04:39:21 +07:00 |
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XMRig
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bea37f59c8
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Added support for alternative CUDA plugin API.
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2019-12-25 00:35:43 +07:00 |
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XMRig
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7d3895f224
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Add console title for Windows.
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2019-12-24 02:04:34 +07:00 |
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XMRig
|
e79740adb5
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Fixed MSVC build.
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2019-12-23 00:37:43 +07:00 |
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XMRig
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9d1a413700
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Add extra variables.
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2019-12-23 00:28:57 +07:00 |
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XMRig
|
2df6f5cd17
|
Added ENV support for "loader" option.
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2019-12-22 19:48:33 +07:00 |
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XMRig
|
f0b441040a
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Added ENV support for "user", "pass" and "rig-id" fields.
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2019-12-22 19:09:30 +07:00 |
|
XMRig
|
976778c12c
|
Added Env class.
|
2019-12-22 18:09:26 +07:00 |
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XMRig
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37adda9421
|
Make Process::location static.
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2019-12-22 13:26:06 +07:00 |
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XMRig
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1c18b3d942
|
Added --randomx-no-rdmsr command line option.
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2019-12-21 23:57:25 +07:00 |
|
XMRig
|
c8e0de5cd7
|
v5.4.1-dev
|
2019-12-21 23:42:18 +07:00 |
|
XMRig
|
fec5a6ecbd
|
v5.4.0
|
2019-12-21 16:12:02 +07:00 |
|
XMRig
|
0a2924529b
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Added extra error message.
|
2019-12-20 23:44:32 +07:00 |
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XMRig
|
a5d13c4e64
|
Allow use old CUDA plugin.
|
2019-12-20 21:10:13 +07:00 |
|
XMRig
|
c0984798b3
|
Add missing algorithm name alias.
|
2019-12-20 04:08:47 +07:00 |
|
XMRig
|
f2f610f0f5
|
Fix OpenCL.
|
2019-12-20 04:05:09 +07:00 |
|
Tony Butler
|
4c4b29d45c
|
Add MoneroV (rx/v) algorithm [based on MoneroOcean/master]
|
2019-12-18 16:17:22 -07:00 |
|
XMRig
|
66a4586559
|
Fixed MsrItem serialization.
|
2019-12-19 03:49:32 +07:00 |
|
XMRig
|
80688c52ec
|
Allow number value for "wrmsr" option only for Intel.
|
2019-12-19 03:28:05 +07:00 |
|
XMRig
|
ddcc9852f7
|
Use MsrItem::kNoMask.
|
2019-12-19 03:20:48 +07:00 |
|
SChernykh
|
18ceec0022
|
Fixed crash with GCC compiler
|
2019-12-18 17:32:57 +01:00 |
|
SChernykh
|
3bb6b332db
|
Fixed AVX detection
|
2019-12-18 12:20:21 +01:00 |
|
SChernykh
|
5492d9270f
|
Update jit_compiler_x86_static.S
|
2019-12-18 09:13:21 +01:00 |
|
SChernykh
|
4237ed6fad
|
Add vzeroupper for processors with AVX
To avoid false dependencies on upper 128 bits of YMM registers.
|
2019-12-18 09:12:25 +01:00 |
|
SChernykh
|
fc3c995ec2
|
Added bit masks for MSR registers
|
2019-12-17 23:55:22 +01:00 |
|
XMRig
|
c2267d3343
|
Less error prone log interface.
|
2019-12-18 02:20:31 +07:00 |
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