Commit Graph

363 Commits

Author SHA1 Message Date
XMRig
730f028343 Add "cn/ultra" alias for tlo-pool.raasu.org pool. 2019-12-29 15:36:05 +07:00
XMRig
d74775d702 Added "cn-pico/tlo". 2019-12-29 00:29:19 +07:00
XMRig
82d4a1b3c9 Fix build. 2019-12-28 02:00:08 +07:00
XMRig
cbcf033ebe Code style cleanup. 2019-12-28 01:45:54 +07:00
SChernykh
a1f223dcb0 Fix for 1st-gen Ryzen crashes 2019-12-27 12:40:38 +02:00
XMRig
a46c4f02e8 Removed "rx/v" algorithm. 2019-12-26 22:34:19 +07:00
XMRig
e7c4b1d0c2 Fixed memory allocation checks. 2019-12-25 04:39:21 +07:00
XMRig
a5d13c4e64 Allow use old CUDA plugin. 2019-12-20 21:10:13 +07:00
XMRig
c0984798b3 Add missing algorithm name alias. 2019-12-20 04:08:47 +07:00
XMRig
f2f610f0f5 Fix OpenCL. 2019-12-20 04:05:09 +07:00
Tony Butler
4c4b29d45c Add MoneroV (rx/v) algorithm [based on MoneroOcean/master] 2019-12-18 16:17:22 -07:00
XMRig
66a4586559 Fixed MsrItem serialization. 2019-12-19 03:49:32 +07:00
XMRig
80688c52ec Allow number value for "wrmsr" option only for Intel. 2019-12-19 03:28:05 +07:00
XMRig
ddcc9852f7 Use MsrItem::kNoMask. 2019-12-19 03:20:48 +07:00
SChernykh
18ceec0022 Fixed crash with GCC compiler 2019-12-18 17:32:57 +01:00
SChernykh
3bb6b332db Fixed AVX detection 2019-12-18 12:20:21 +01:00
SChernykh
5492d9270f Update jit_compiler_x86_static.S 2019-12-18 09:13:21 +01:00
SChernykh
4237ed6fad Add vzeroupper for processors with AVX
To avoid false dependencies on upper 128 bits of YMM registers.
2019-12-18 09:12:25 +01:00
SChernykh
fc3c995ec2 Added bit masks for MSR registers 2019-12-17 23:55:22 +01:00
XMRig
c2267d3343 Less error prone log interface. 2019-12-18 02:20:31 +07:00
XMRig
59a3d8c530 Added "verbose" option. 2019-12-17 21:46:11 +07:00
XMRig
f2ef200128 Merge branch 'feature-custom-msr' into dev 2019-12-17 16:53:28 +07:00
XMRig
9d67221f54 Added save/restore MSR registers on Linux. 2019-12-17 16:17:11 +07:00
XMRig
e0a9c69ab9 Rename Rx_windows.cpp to Rx_win.cpp. 2019-12-17 15:16:37 +07:00
XMRig
b25d6d5f67 Added RandomX option "rdmsr" and save/restore MSR registers on Windows. 2019-12-17 14:45:01 +07:00
XMRig
efb63d15e1 Added support for write custom MSR. 2019-12-17 02:27:07 +07:00
SChernykh
9b5ccb55a5 RandomSFX (Safex Cash variant) support 2019-12-16 19:36:29 +01:00
XMRig
28c9cdd4da #1423 Implemented driver reuse. 2019-12-16 03:41:58 +07:00
XMRig
2f6432751c Strict wrmsr error handling. 2019-12-16 02:45:07 +07:00
XMRig
ca8708319f Revert changes. 2019-12-16 02:17:57 +07:00
SChernykh
a1d359f045 Use unique service name for WinRing0 driver
To avoid error 1072
2019-12-15 19:28:14 +01:00
XMRig
34f84582d0 Removed unnecessary check. 2019-12-15 12:02:45 +07:00
XMRig
3fad0b0c31 Added missing tag. 2019-12-15 01:52:20 +07:00
XMRig
6d9e1a50cc Unified Linux/Windows MSR log messages. 2019-12-15 01:32:41 +07:00
SChernykh
53919c1281 Fixed thread count for MSR mod 2019-12-14 16:30:46 +01:00
SChernykh
5cf846b28d MSR mod for Windows 2019-12-14 16:04:37 +01:00
XMRig
2f19cddc9f Added additional MSR registers for Ryzen CPUs. 2019-12-12 14:21:15 +07:00
XMRig
86e5ab861b Don't build Rx_linux.cpp on ARM. 2019-12-11 21:20:37 +07:00
XMRig
6d176d2013 Fixed MSR. 2019-12-11 20:09:25 +07:00
XMRig
7a507a2c8a Added support for AMD specific MSR registers. 2019-12-11 19:37:13 +07:00
XMRig
79a7d91166 Fixed --randomx-wrmsr option without parameters. 2019-12-11 19:16:01 +07:00
XMRig
f960d1cf16 Added RandomX option "wrmsr" with command line equivalent --randomx-wrmsr=N. 2019-12-10 23:57:29 +07:00
SChernykh
9629001fe4 Update jit_compiler_x86_static.S 2019-12-09 20:30:37 +01:00
SChernykh
7e724aa70d More optimizations for Ryzen 2019-12-09 20:29:05 +01:00
SChernykh
e35ce64e14 Fixed assembly selection for RandomX when it's on Auto 2019-12-09 18:59:49 +01:00
XMRig
fbd39ca49d Move "1gb-pages" option to "randomx" object. 2019-12-09 21:42:40 +07:00
XMRig
280618a9eb Memory allocation refactoring. 2019-12-08 23:17:39 +07:00
SChernykh
08eef1bf9a Fix GCC compilation 2019-12-08 16:51:37 +01:00
SChernykh
8a1679ec89 Fixed indentation 2019-12-08 16:20:46 +01:00
SChernykh
2ed2629653 Optimized dataset read for Ryzen CPUs
Removed register dependency in dataset read, +0.8% speedup on average.
2019-12-08 16:14:02 +01:00