XMRig
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730f028343
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Add "cn/ultra" alias for tlo-pool.raasu.org pool.
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2019-12-29 15:36:05 +07:00 |
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XMRig
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d74775d702
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Added "cn-pico/tlo".
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2019-12-29 00:29:19 +07:00 |
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XMRig
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82d4a1b3c9
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Fix build.
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2019-12-28 02:00:08 +07:00 |
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XMRig
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cbcf033ebe
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Code style cleanup.
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2019-12-28 01:45:54 +07:00 |
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SChernykh
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a1f223dcb0
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Fix for 1st-gen Ryzen crashes
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2019-12-27 12:40:38 +02:00 |
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XMRig
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a46c4f02e8
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Removed "rx/v" algorithm.
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2019-12-26 22:34:19 +07:00 |
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XMRig
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e7c4b1d0c2
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Fixed memory allocation checks.
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2019-12-25 04:39:21 +07:00 |
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XMRig
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a5d13c4e64
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Allow use old CUDA plugin.
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2019-12-20 21:10:13 +07:00 |
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XMRig
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c0984798b3
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Add missing algorithm name alias.
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2019-12-20 04:08:47 +07:00 |
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XMRig
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f2f610f0f5
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Fix OpenCL.
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2019-12-20 04:05:09 +07:00 |
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Tony Butler
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4c4b29d45c
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Add MoneroV (rx/v) algorithm [based on MoneroOcean/master]
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2019-12-18 16:17:22 -07:00 |
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XMRig
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66a4586559
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Fixed MsrItem serialization.
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2019-12-19 03:49:32 +07:00 |
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XMRig
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80688c52ec
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Allow number value for "wrmsr" option only for Intel.
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2019-12-19 03:28:05 +07:00 |
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XMRig
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ddcc9852f7
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Use MsrItem::kNoMask.
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2019-12-19 03:20:48 +07:00 |
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SChernykh
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18ceec0022
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Fixed crash with GCC compiler
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2019-12-18 17:32:57 +01:00 |
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SChernykh
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3bb6b332db
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Fixed AVX detection
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2019-12-18 12:20:21 +01:00 |
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SChernykh
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5492d9270f
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Update jit_compiler_x86_static.S
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2019-12-18 09:13:21 +01:00 |
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SChernykh
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4237ed6fad
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Add vzeroupper for processors with AVX
To avoid false dependencies on upper 128 bits of YMM registers.
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2019-12-18 09:12:25 +01:00 |
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SChernykh
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fc3c995ec2
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Added bit masks for MSR registers
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2019-12-17 23:55:22 +01:00 |
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XMRig
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c2267d3343
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Less error prone log interface.
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2019-12-18 02:20:31 +07:00 |
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XMRig
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59a3d8c530
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Added "verbose" option.
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2019-12-17 21:46:11 +07:00 |
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XMRig
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f2ef200128
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Merge branch 'feature-custom-msr' into dev
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2019-12-17 16:53:28 +07:00 |
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XMRig
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9d67221f54
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Added save/restore MSR registers on Linux.
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2019-12-17 16:17:11 +07:00 |
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XMRig
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e0a9c69ab9
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Rename Rx_windows.cpp to Rx_win.cpp.
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2019-12-17 15:16:37 +07:00 |
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XMRig
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b25d6d5f67
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Added RandomX option "rdmsr" and save/restore MSR registers on Windows.
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2019-12-17 14:45:01 +07:00 |
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XMRig
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efb63d15e1
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Added support for write custom MSR.
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2019-12-17 02:27:07 +07:00 |
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SChernykh
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9b5ccb55a5
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RandomSFX (Safex Cash variant) support
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2019-12-16 19:36:29 +01:00 |
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XMRig
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28c9cdd4da
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#1423 Implemented driver reuse.
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2019-12-16 03:41:58 +07:00 |
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XMRig
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2f6432751c
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Strict wrmsr error handling.
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2019-12-16 02:45:07 +07:00 |
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XMRig
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ca8708319f
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Revert changes.
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2019-12-16 02:17:57 +07:00 |
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SChernykh
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a1d359f045
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Use unique service name for WinRing0 driver
To avoid error 1072
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2019-12-15 19:28:14 +01:00 |
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XMRig
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34f84582d0
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Removed unnecessary check.
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2019-12-15 12:02:45 +07:00 |
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XMRig
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3fad0b0c31
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Added missing tag.
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2019-12-15 01:52:20 +07:00 |
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XMRig
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6d9e1a50cc
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Unified Linux/Windows MSR log messages.
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2019-12-15 01:32:41 +07:00 |
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SChernykh
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53919c1281
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Fixed thread count for MSR mod
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2019-12-14 16:30:46 +01:00 |
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SChernykh
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5cf846b28d
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MSR mod for Windows
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2019-12-14 16:04:37 +01:00 |
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XMRig
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2f19cddc9f
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Added additional MSR registers for Ryzen CPUs.
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2019-12-12 14:21:15 +07:00 |
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XMRig
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86e5ab861b
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Don't build Rx_linux.cpp on ARM.
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2019-12-11 21:20:37 +07:00 |
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XMRig
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6d176d2013
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Fixed MSR.
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2019-12-11 20:09:25 +07:00 |
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XMRig
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7a507a2c8a
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Added support for AMD specific MSR registers.
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2019-12-11 19:37:13 +07:00 |
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XMRig
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79a7d91166
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Fixed --randomx-wrmsr option without parameters.
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2019-12-11 19:16:01 +07:00 |
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XMRig
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f960d1cf16
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Added RandomX option "wrmsr" with command line equivalent --randomx-wrmsr=N.
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2019-12-10 23:57:29 +07:00 |
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SChernykh
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9629001fe4
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Update jit_compiler_x86_static.S
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2019-12-09 20:30:37 +01:00 |
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SChernykh
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7e724aa70d
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More optimizations for Ryzen
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2019-12-09 20:29:05 +01:00 |
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SChernykh
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e35ce64e14
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Fixed assembly selection for RandomX when it's on Auto
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2019-12-09 18:59:49 +01:00 |
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XMRig
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fbd39ca49d
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Move "1gb-pages" option to "randomx" object.
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2019-12-09 21:42:40 +07:00 |
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XMRig
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280618a9eb
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Memory allocation refactoring.
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2019-12-08 23:17:39 +07:00 |
|
SChernykh
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08eef1bf9a
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Fix GCC compilation
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2019-12-08 16:51:37 +01:00 |
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SChernykh
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8a1679ec89
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Fixed indentation
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2019-12-08 16:20:46 +01:00 |
|
SChernykh
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2ed2629653
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Optimized dataset read for Ryzen CPUs
Removed register dependency in dataset read, +0.8% speedup on average.
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2019-12-08 16:14:02 +01:00 |
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