SChernykh
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e3828a13f9
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Fixed crashes on ARM
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2021-02-01 17:07:45 +01:00 |
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xmrig
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0da777bfe3
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Merge pull request #2058 from SChernykh/dev
RandomX JIT x86: remove unnecessary instructions
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2021-01-24 13:59:56 +07:00 |
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SChernykh
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787aad0d62
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RandomX JIT x86: remove unnecessary instructions
Adopted from https://github.com/tevador/RandomX/pull/201
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2021-01-23 22:28:50 +01:00 |
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XMRig
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0444103fba
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Fixed Cache QoS restore on exit where it not supported.
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2021-01-24 02:23:27 +07:00 |
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XMRig
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61d5f1aacb
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Added RxMsr class.
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2021-01-23 23:23:39 +07:00 |
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XMRig
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8a64a827f7
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Move Ryzen related fixes to RxFix class.
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2021-01-23 00:27:56 +07:00 |
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XMRig
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0273ea7140
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Added new class Msr.
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2021-01-22 23:50:25 +07:00 |
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XMRig
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5c7d9447ed
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Merge branch 'master' into feature-msr2
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2021-01-22 16:55:57 +07:00 |
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XMRig
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647af97d75
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#2043 Fix compile warning.
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2021-01-17 17:48:35 +07:00 |
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Richard Mitsuk Lavitt
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a8cbc72fd1
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fixed grammar in a couple of awkward error messages
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2021-01-15 14:33:38 -06:00 |
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SChernykh
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fac3902ae1
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RandomX x86 JIT: remove redundant CFROUND
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2021-01-07 16:20:00 +01:00 |
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SChernykh
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90760db1c9
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Fix GCC warning
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2020-12-19 19:50:52 +01:00 |
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SChernykh
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7d92d57059
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Another dataset AVX2 init speedup (+3.8% faster on Zen3)
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2020-12-19 19:46:31 +01:00 |
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SChernykh
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0319b5b622
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Added config option for AVX2 dataset init
-1 = Auto detect
0 = Always disabled
1 = Enabled if AVX2 is supported
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2020-12-19 16:18:49 +01:00 |
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SChernykh
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eae3a62345
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Auto-detect the fastest code for dataset init
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2020-12-19 13:59:28 +01:00 |
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SChernykh
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aaf1ed1c99
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Dataset initialization with AVX2 (WIP)
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2020-12-18 14:53:54 +01:00 |
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XMRig
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f169227ebd
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Huge pages not supported by macOS ARM.
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2020-12-16 01:59:20 +07:00 |
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XMRig
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e706936763
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Reduce JIT memory for ARM.
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2020-12-15 02:52:38 +07:00 |
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SChernykh
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b89d432b7d
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Fix alignment for Linux
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2020-12-14 18:32:25 +01:00 |
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SChernykh
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e3dc83e383
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Fix: secure JIT and huge pages are incompatible on Windows
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2020-12-14 18:22:58 +01:00 |
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XMRig
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3b39725737
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Fixed JIT on macOS.
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2020-12-12 22:40:48 +07:00 |
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XMRig
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e7a26413a8
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Fixed macOS build.
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2020-12-12 22:15:15 +07:00 |
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XMRig
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ef691ee323
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Alternative secure JIT for macOS.
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2020-12-12 21:32:36 +07:00 |
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XMRig
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25a9fb2ab4
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Fixed secure JIT on Linux and code cleanup.
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2020-12-12 19:18:47 +07:00 |
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XMRig
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df3831d6f6
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Remove duplicated code.
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2020-12-12 12:39:11 +07:00 |
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XMRig
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84443a4e8b
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Added generic secure JIT support for RandomX.
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2020-12-11 23:17:54 +07:00 |
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SChernykh
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83d152f557
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More static analysis fixes
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2020-12-08 16:05:58 +01:00 |
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SChernykh
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d5f84a813d
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Fixed errors found by static analysis
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2020-12-08 12:16:59 +01:00 |
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XMRig
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4569eea6f6
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Move Profiler and more cleanup.
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2020-12-04 09:23:40 +07:00 |
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XMRig
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c8ebffd012
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Added Cvt class.
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2020-12-02 16:31:45 +07:00 |
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SChernykh
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78dba13722
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Fix RandomX init when switching to other algo and back
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2020-11-29 22:02:48 +01:00 |
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SChernykh
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dfc4f40026
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Optimized JIT compiler
More branch-free code
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2020-11-29 14:05:50 +01:00 |
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SChernykh
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76c406ce63
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Make single thread bench cheat-resistant
Each hash is dependent on the previous hash to make multi-threaded cheating impossible.
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2020-11-15 20:38:27 +01:00 |
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SChernykh
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bdb6fe7d05
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Fixed MSR mod names in JSON API
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2020-11-14 19:55:43 +01:00 |
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XMRig
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6e0e0fe22a
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#1937 Print path to existing WinRing0 service without verbose option.
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2020-11-12 23:32:49 +07:00 |
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cohcho
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5e0e7a7c72
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MemoryPool: fix alignment modification
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2020-11-10 16:49:10 +00:00 |
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cohcho
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f556a69e7f
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CompiledVm: define default constructor
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2020-11-09 16:29:42 +00:00 |
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SChernykh
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648fa6f164
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Separate MSR mod for Zen/Zen2 and Zen3
Another +0.5% speedup for Zen2
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2020-11-08 19:40:44 +01:00 |
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xmrig
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ba486a2e2b
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Merge pull request #1932 from SChernykh/dev
New MSR mod for Ryzen
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2020-11-07 13:09:21 +07:00 |
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SChernykh
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3fe06970b0
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Update RxConfig.cpp
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2020-11-06 22:59:18 +01:00 |
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SChernykh
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dc2a6ebd32
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New MSR mod for Ryzen
+3.5% on Zen2, +1-2% on Zen3
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2020-11-06 22:56:09 +01:00 |
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XMRig
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856686a529
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#1918 Fixed check for 1GB huge pages on ARM Linux.
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2020-11-02 21:26:35 +07:00 |
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SChernykh
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4706136148
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Fix compilation on ARMv8 with GCC 9.3.0
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2020-11-02 13:50:10 +01:00 |
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XMRig
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66e7951d2b
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Merge branch 'feature-bench-submit' into dev
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2020-10-30 23:25:09 +07:00 |
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SChernykh
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21022fe226
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Also fix RelWithDebIfno build in Visual Studio
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2020-10-27 14:25:43 +01:00 |
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SChernykh
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d822ffef36
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Fixed Debug build in Visual Studio
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2020-10-27 14:08:36 +01:00 |
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XMRig
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34a9aaf358
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Added "msr" field for CPU backend.
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2020-10-25 16:36:37 +07:00 |
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cohcho
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020d4acba2
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MSR: supress kernel module warning
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2020-10-23 13:09:13 +00:00 |
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XMRig
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c5b118ab4c
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New Async wrapper.
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2020-10-21 08:09:44 +07:00 |
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XMRig
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572616f3d2
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Code cleanup.
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2020-10-16 19:35:36 +07:00 |
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