Add `./build.sh --macos-release`, producing a portable host-arch macOS
binary (Intel x86_64 or Apple Silicon arm64). libuv, hwloc, and OpenSSL
are linked statically from Homebrew so the result runs on stock macOS
without Homebrew at runtime.
Homebrew's static libhwloc.a is built with the libxml2 and OpenCL
topology plugins, so the link adds `-lxml2 -framework OpenCL` (both
ship with macOS). Brew prefixes are resolved via `brew --prefix`, so
the same target works on Intel (/usr/local) and Apple Silicon
(/opt/homebrew); the package is named by `uname -m`.
Also document the macOS build in README and ignore build-macos/.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Switch fork versioning from 6.25.1-drg2 to a clean 6.25.2 patch version
(APP_VERSION, APP_VER_PATCH, package.json, CHANGELOG heading).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The bundled config had a portless pool URL (pool.dragonx.is), so xmrig
fell back to its default port 3333, which is firewalled on the pool host
-> repeating 'connect error: operation canceled'. The pool's stratum is
plain TCP on 3433 and requires a shielded zs-address worker name.
- src/config.example.json: url -> pool.dragonx.is:3433, algo -> rx/dragonx,
user placeholder -> YOUR_DRGX_ZS_ADDRESS
- scripts/pool_mine_example.cmd: point at the DragonX pool with rx/dragonx
- scripts/build_windows.sh: fetch OpenSSL 1.1.1w from GitHub release mirror
- bump APP_VERSION to 6.25.1-drg2
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Wire parity with miner113/xmrig: the algo string reported and sent in
submits is now rx/dragonx; rx/hush, randomx/dragonx, dragonx, etc. remain
accepted aliases so existing configs keep working.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
- POOL_INTEGRATION.md: exact job/submit format, pool-side validation &
scoring on the SHA256D pow-hash, and a zero-downtime dual-accept rollout
plan (deploy dual-accept pool before announcing drg-xmrig).
- Restore doc/build/ docs removed during the initial copy.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Port miner113's RX_DRAGONX mining model into the RX_HUSH path so DragonX
mining is identical in solo and pool mode:
- CpuWorker: filter EVERY hash on SHA256D(header + RandomX solution) (the
block-bearing pow-hash) instead of the RandomX hash; submit the full
32-byte nonce + rx_hash. Removes the fragile pool-mode dual-check that
was dropping ~half of block candidates.
- Job: 32-byte nonce for RX_HUSH in pool mode too (was solo-only).
- JobResult: populate nonceBytes() on the standard 4-byte path.
- Client: submit a variable-width nonce (32-byte for DragonX) with a
dynamically laid-out temp buffer.
Effect: shares and blocks use one metric, so the pool receives every block
candidate (no under-submission gap) and the hashrate is block-relevant.
Rebrand to drg-xmrig (version.h, build.sh, package.json, README) + add
PROTOCOL.md wire spec.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Pool sends block_target (full 256-bit network target) with each job.
Miner checks SHA256D(header + RandomX solution) for every hash against
the block target, enabling block detection at full hashrate instead of
only on submitted shares.
- Switch from full-block to header-only (140-byte) RandomX input
- Add 32-byte SoloNonce system for solo mining mode
- Compute proper difficulty target from compact bits field
- Add SHA256D dual-hash PoW check in CpuWorker for solo mining
- Raise RandomX dataset/scratchpad limits to 4GB/4MB
- Use standard RandomX share filtering in pool (stratum) mode
- Add DragonX coin and rx/hush algorithm support
- Update branding to XMRig-HAC / dragonx.is
- Update repository URLs to git.hush.is
- Replace example wallet addresses with placeholders
- Update .gitignore for build directories
- Document fork changes in README and CHANGELOG
armv8l is what CMAKE_SYSTEM_PROCESSOR is set to when an ARMv8 processor
is in 32-bit mode, so it should be added to the ARMv7 target list even
though it's v8 because it's 32 bits. Currently, it's not in any ARM
target list which means x86 is assumed and the build fails.
