DragonX/xmrig-hac
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Author SHA1 Message Date
XMRig
cb63e8e7d0 Better v1 PoW implementation, added variant option. 2018-03-12 22:29:44 +07:00
XMRig
668e38aaf7 Some small fixes. 2018-03-12 14:44:23 +07:00
XMRig
9a09a90e2a Change donation address to separate old and new versions. 2018-03-09 13:15:55 +07:00
XMRig
ca94598078 v2.5.0-dev 2018-03-09 01:49:24 +07:00
XMRig
55e56bc95b Revert changes in Api class, single threaded http server will not be included in 2.5 release. 2018-03-09 01:47:44 +07:00
XMRig
81a20e6e2c Merge branch 'vtnerd-monero-v1-pow' into dev 
# Conflicts:
#	src/api/Httpd.cpp
#	src/api/Httpd.h
 2018-03-09 01:41:47 +07:00
xmrig
78ba0a355f Update CHANGELOG.md 2018-03-09 01:30:32 +07:00
xmrig
737e2cb83d Update CHANGELOG.md 2018-03-09 00:56:29 +07:00
XMRig
1d6ffa3e8d Added coin field support added in xmrig-proxy 2.5. 2018-03-09 00:50:06 +07:00
XMRig
a8b1f84e30 Automatically enable nicehash when use with upcoming xmrig-proxy 2.5. 2018-03-07 21:56:43 +07:00
XMRig
e77c7a9824 Added option to disable Monero v7 PoW, may useful in future if other coins update their network to v7 without PoW change. 2018-03-07 19:12:18 +07:00
XMRig
aa0e556318 Added full IPv6 support. 2018-03-07 16:38:58 +07:00
XMRig
77a9087f3f Added reference hashes. 2018-03-07 15:32:44 +07:00
XMRig
fac912767c PoW changes WIP 2018-03-06 21:34:20 +07:00
XMRig
8a6f0f1e4d Update copyright and move version into Job class. 2018-03-06 17:06:07 +07:00
XMRig
ef42dbeeec Merge branch 'monero-v1-pow' of https://github.com/vtnerd/xmrig into vtnerd-monero-v1-pow 2018-03-06 16:37:33 +07:00
XMRig
7f6b5a3fd2 Fixed regression (all versions since 2.4 affected) fragmented responses from pool/proxy parsed incorrectly. 2018-03-05 13:54:21 +07:00
XMRig
c735c157e4 #428 Fixed regression with CPU cache size detection. 2018-03-05 02:15:05 +07:00
Lee Clagett
6f4fbb3c40 Changes for the Monero v1 PoW 2018-03-02 22:17:29 +00:00
XMRig
30515aa6b6 Use adaptive timer instead of idle handler for HTTP server. 2018-03-01 09:53:27 +07:00
XMRig
bc0e9c2d02 Added XMRIG_DEPS cmake variable for unified dependencies. 2018-02-21 00:52:52 +07:00
XMRig
bf9e84f4b7 Run internal http server in main loop to avoid requirement to thread synchronization. 2018-02-20 23:22:34 +07:00
XMRig
1d72acad97 Merge branch 'master' into dev 2018-02-20 22:48:39 +07:00
xmrig
3ebff4137c Update CHANGELOG.md 2018-02-19 15:58:44 +07:00
XMRig
def56d5233 v2.4.5 RC 2018-02-19 04:31:50 +07:00
xmrig
968365ffc5 Update README.md 2018-02-19 04:17:50 +07:00
xmrig
e5ffa34206 Update README.md 2018-02-18 05:49:37 +07:00
xmrig
5c598ef545 Merge pull request #379 from DeadManWalkingTO/master 
Update README.md
 2018-02-18 05:48:09 +07:00
xmrig
2cce6e0c72 Update CHANGELOG.md 2018-02-18 05:32:36 +07:00
xmrig
2cb4424f99 Update README.md 2018-02-18 05:06:10 +07:00
XMRig
2571fd1958 Merge branch 'master' of github.com:xmrig/xmrig 2018-02-08 17:35:20 +07:00
XMRig
c434312be6 Merge branch 'Foudge-master' 2018-02-08 17:34:33 +07:00
XMRig
8a3b8ff788 Fix code style, replace tabs to space #2. 2018-02-08 17:21:12 +07:00
XMRig
9cf2b0a782 Fix code style, replace tabs to space. 2018-02-08 17:02:32 +07:00
XMRig
640592ad95 Merge branch 'master' of https://github.com/Foudge/xmrig into Foudge-master 2018-02-08 16:56:20 +07:00
Foudge
0184647f7e Correct L2 cache size calculation for Intel Core 2 family 
This is a workaround for total L2 cache size calculation of Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue. These processors have L2 cache shared by 2 cores.

There is maybe more CPU with L2 shared cache, but I am sure that these models are concerned and they are not so numerous.
A better way would be to modify libcpuid to implement L2 cache counting.
 2018-02-03 16:31:13 +01:00
DeadManWalking
8f61bd5f58 Update README.md 2018-02-02 00:58:11 +02:00
DeadManWalking
3d464088ae Update README.md 2018-02-02 00:54:58 +02:00
DeadManWalking
4abec1e177 Update README.md 2018-02-02 00:14:39 +02:00
DeadManWalking
1dad11068e Merge pull request #1 from xmrig/master 
!
 2018-02-01 23:02:32 +02:00
Foudge
8869ede7b5 Compilation error under FreeBSD 
ULONG is not recognized under this OS, so replaced it with more portable definition.
 2018-01-28 18:13:00 +01:00
Foudge
50e4f9e3e7 up to 20% perf increase with Cryptonight with non-AES CPU 
This time, the performance increase is got with MSVC and GCC. On non-AES CPU, there were an useless load/store SSE2 register. The last MSVC "hack" is replaced by a portable code and he's more complete (a load is saved).

On my C2Q6600, with 3 thread, I have +16% with MSVC2015 and +20% with GCC 7.3, compared to official 2.4.4 version.
 2018-01-28 12:58:19 +01:00
Foudge
107cf54513 Remove compilation warnings under MSVC 2018-01-27 11:42:22 +01:00
xmrig
8ce7b1fd54 Merge pull request #353 from Foudge/master 
up to 15% boost on CryptoNight algo with non-AES CPU
 2018-01-26 00:53:22 +07:00
XMRig
fd4e37bee7 #341 Added option --dry-run. 2018-01-20 20:43:31 +07:00
Foudge
7c79ecb786 +15% boost with non-AES CPU 
Performance boost validated on Core 2 Quad processor under Windows 10.
But it's Windows/MS Visual C++ specific.
 2018-01-20 10:43:56 +01:00
XMRig
d099bef71f #341 Fix wrong exit code. 2018-01-20 12:58:43 +07:00
xmrig
357d2cb9f0 Merge pull request #324 from stanz2g/master 
can build without microhttpd when WITH_HTTPD=OFF
 2018-01-20 01:35:12 +07:00
xmrig
6352881fe6 Update CHANGELOG.md 2018-01-11 15:08:24 +07:00
XMRig
f8481a4430 #328 Added guard to prevent paused message spam and crash. 2018-01-10 22:55:45 +07:00